Intel 8XC196NT, User Manual

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8XC196NT USER’S MANUAL
14-40
Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pair
indicate a signal and its condition, respectively. Symbols represent the time between the two sig-
nal/condition points. For example,
T
LLRL
is the time between signal L (ALE/ADV#) condition L
(Low) and signal R (RD#) condition L (Low). Table 14-8 defines the signal and condition codes.
Table 14-9 defines the AC timing specifications that the memory system must meet and those that
the device will provide.
Table 14-8. AC Timing Symbol Definitions
Signals Conditions
A Address G BUSWIDTH R RD# H High
B BHE# H HOLD# W WR#, WRH#, WRL# L Low
BR BREQ# HA HLDA# X XTAL1 V Valid
C CLKOUT L ALE/ADV# Y READY X No Longer Valid
D DATA Q Data Out Z Floating
Table 14-9. AC Timing Definitions
Symbol Definition
The External Memory System Must Meet These Specifications
T
AVDV
Address Valid to Input Data Valid
Maximum time the memory device has to output valid data after the 8XC196NT outputs a valid
address.
T
RHDZ
RD# High to Input Data Float
Time after RD# is inactive until the memory system must float the bus. If this timing is not met,
bus contention will occur.
T
RLDV
RD# Low to Input Data Valid
Maximum time the memory system has to output valid data after the 8XC196NT asserts RD#.
The 8XC196NT Meets These Specifications
T
OSC
1/F
XTAL
All AC timings are referenced to T
OSC
.
T
AVLL
Address Setup to ALE/ADV# Low
Length of time address is valid before ALE/ADV# falls. Use this specification when designing
the external latch.
T
CHCL
CLKOUT High Period
Needed in systems that use CLKOUT as clock for external devices.
T
CHLH
CLKOUT High to ALE/ADV# High (modes 1 and 2 only)
Time between CLKOUT going high and ALE/ADV# going high. Use to derive other timings.
T
CLCL
CLKOUT Cycle Time
Normally 2 T
OSC
.