Intel 8XC196NT, User Manual

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8XC196NT USER’S MANUAL
10-32
INIT_INTERRUPTS:
LD JTBASE_PTR,#LSW JTBASE ;store jump table base address
EPAx_ISR:
LD EPAIPV_PTR,#EPAIPV ;read EPAIPV offset
PUSHA ;save INT_MASK/INT_MASK1/WSR/PSW
TIJMP JTBASE_PTR,[EPAIPV_PTR],#1FH ;initiate jump to correct ISR
OVR_EPA0_ISR: ;EPA0 overrun routine
. ;
. ;
TIJMP JTBASE_PTR,[EPAIPV_PTR],#1FH
;check for pending
;interrupts, exit
EPAx_DONE:
POPA
RET
;exit, all EPAx
;interrupts serviced
JTBASE:
DCW LSW EPAx_done ;0 (no interrupt pending)
DCW LSW OVR_TM2_ISR ;1 (Timer2 overflow)
DCW LSW OVR_TM1_ISR ;2 (Timer1 overflow)
DCW .
DCW .
DCW .
DCW LSW OVR_EPA0_ISR ;0EH (EPA0 overflow)
This example assumes that EPAx is enabled, OVR0 is enabled, interrupts are globally enabled,
and the capture/compare channel 0 has generated an OVR0 interrupt. This interrupt occurs when
an edge is detected on the EPA channel and both the input buffer and EPA0_TIME are full. This
causes software to enter the EPAx_ISR interrupt service routine.
Note that index_mask is set to 1FH. This sets the pointer to the end of the jump table to prevent
software from jumping to an invalid address. Changing index_mask can dictate software control,
thus superseding interrupt priorities.
Note that instead of a RET instruction at the end of OVR_EPA0_ISR, another TIJMP instruction
is used. This is done to check for any other pending multiplexed interrupts. If EPAIPV contains
a zero value (no pending interrupts) a vector to EPAx_DONE occurs and a RET is executed. This
is to ensure that EPAIPV is cleared before the routine returns from the EPAx_ISR.