Intel 8XC196NT, User Manual

Page: 526 / 597

C-31
REGISTERS
INT_MASK
INT_MASK
Address:
Reset State:
0008H
00H
The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests.
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the
low byte of the processor status word (PSW); therefore, PUSHF or PUSHA saves this register on the
stack and POPF or POPA restores it.
7 0
IBF OBE AD EPA0 EPA1 EPA2 EPA3 EPA x
Bit
Number
Function
7:0 Setting a bit enables the corresponding interrupt.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt Standard Vector
IBF Slave Port Input Buffer Full FF200EH
OBE Slave Port Output Buffer Empty FF200CH
AD A/D Conversion Complete FF200AH
EPA0 EPA Capture/Compare Channel 0 FF2008H
EPA1 EPA Capture/Compare Channel 1 FF2006H
EPA2 EPA Capture/Compare Channel 2 FF2004H
EPA3 EPA Capture/Compare Channel 3 FF2002H
EPA
x
†
Multiplexed EPA FF2000H
†
EPA 4–9 capture/compare channel events, EPA 0–1 compare channel events, EPA 0–9
capture/compare overruns, and timer overflows can generate this multiplexed interrupt.
The EPA mask and pending registers decode the EPA
x
interrupt. Write the EPA mask
registers (EPA_MASK and EPA_MASK1) to enable the interrupt sources; read the EPA
pending registers (EPA_PEND and EPA_PEND1) to determine which source caused the
interrupt.