Intel 8XC196NT, User Manual

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8XC196NT USER’S MANUAL
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3 STE Single Transfer Enable
Enables and disables transfer of a single byte. Unless ATR is set, STE is
automatically cleared at the end of a transfer. The THS, STE, and ATR
bits must be set for handshaking modes.
0 = disable transfers
1 = allow transmission or reception of a single byte
2 ATR Automatic Transfer Re-enable
Enables and disables subsequent transfers. The THS, STE, and ATR bits
must be set for handshaking modes.
0 = allow automatic clearing of STE; disable subsequent transfers
1 = prevent automatic clearing of STE; allow transfer of next byte
1 OUF Overflow/Underflow Flag
Indicates whether an overflow or underflow has occurred. An attempt to
access SSIO
x _BUF during a byte transfer sets this bit.
For the master (M/S# = 1)
0 = no overflow or underflow has occurred
1 = the core attempted to access SSIO
x _BUF during the current transfer
For the slave (M/S# = 0)
0 = no overflow or underflow has occurred
1 = the core attempted to access SSIO
x _BUF during the current transfer
or the master attempted to clock data into or out of the slave’s
SSIO
x _BUF before the buffer was available
0 TBS Transceiver Buffer Status
Indicates the status of the channel’s SSIO x _BUF.
For the transmitter (T/R# =1)
0 = SSIO x _BUF is full; waiting to transmit
1 = SSIO x _BUF is empty; buffer available
For the receiver (T/R# = 0)
0 = SSIO x _BUF is empty; waiting to receive
1 = SSIO x _BUF is full; data available
SSIO
x
_CON (Continued)
x = 0–1
Address: 1FB1H, 1FB3H
Reset State: 00H
The synchronous serial control x (SSIO x _CON) registers control the communications mode and
handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred
and whether the channel is ready to transmit or receive.
7 0
M/S# T/R# TRT THS STE ATR OUF TBS
Bit
Number
Bit
Mnemonic
Function
†
The M/S# and T/R# bits specify four possible configurations: master transmitter, master receiver,
slave transmitter, or slave receiver.
Figure 8-6. Synchronous Serial Control x (SSIOx_CON) Registers (Continued)