Intel 8XC196NT, User Manual

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8XC196NT USER’S MANUAL
10-12
Figure 10-7. Valid EPA Input Events
An input capture event does not set the interrupt pending bit until the captured time value actually
moves from the capture buffer into the EPAx_TIME register. If the buffer contains data and the
PTS is used to service the interrupts, then two PTS interrupts occur almost back-to-back (that is,
with one instruction executed between the interrupts).
10.4.1.1 Handling EPA Overruns
Overruns occur when an EPA input transitions at a rate that cannot be handled by the EPA inter-
rupt service routine. If no overrun handling strategy is in place, and if the following three condi-
tions exist, a situation may occur where both the capture buffer and the EPAx_TIME register
contain data, and no EPA interrupt is generated.
•
an input signal with a frequency high enough to cause overruns is present on an enabled
EPA pin, and
•
the overwrite bit is set (EPAx_CON.0 = 1; old data is overwritten on overrun), and
•
the EPAx_TIME register is read at the exact instant that the EPA recognizes the captured
edge as valid.
Table 10-4. Action Taken when a Valid Edge Occurs
Overwrite Bit
(EPA x _CON.0)
Status of
Capture Buffer
& EPA x _TIME
Action taken when a valid edge occurs
0 empty Edge is captured and event time is loaded into the capture buffer and
EPA
x _TIME register.
0 full New data is ignored — no capture, EPA interrupt, or transfer occurs;
OVR
x
interrupt pending bit is set.
1 empty Edge is captured and event time is loaded into the capture buffer and
EPA
x _TIME register.
1 full Old data is overwritten in the capture buffer; OVR x interrupt pending
bit is set.
A3130-01
Event 1
2 State
Times
2 State
Times
Event 2
2 State
Times
2 State
Times