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14-21
INTERFACING WITH EXTERNAL MEMORY
When the external device is finished with the bus, it relinquishes control by driving HOLD# high.
In response, the 8XC196NT drives HLDA# high and assumes control of the bus.
If the 8XC196NT has a pending external bus cycle while it is in hold, it asserts BREQ# to request
control of the bus. After the external device responds by driving HOLD# high, the 8XC196NT
exits hold and then deasserts BREQ# and HLDA#.
NOTE
If the 8XC196NT receives an interrupt request while it is in hold, the
8XC196NT asserts INTOUT# only if it is executing from internal memory. If
the 8XC196NT needs to access external memory, it asserts BREQ# and waits
until the external device deasserts HOLD# to assert INTOUT#. If the
8XC196NT receives an interrupt request as it is going into hold (between the
time that an external device asserts HOLD# and the time that the 8XC196NT
responds with HLDA#), the 8XC196NT asserts HLDA# and INTOUT# and
waits until the external device deasserts HOLD# to deassert HLDA# and
INTOUT#.
14.6.1 Enabling the Bus-hold Protocol
To use the bus-hold protocol, you must configure P2.3/BREQ#, P2.5/HOLD#, and P2.6/HLDA#
to operate as special-function signals. BREQ# and HLDA# are active-low outputs; HOLD# is an
active-low input.
You must also set the hold enable bit (HLDEN) in the window selection register (WSR.7) to en-
able the bus-hold protocol. Once the bus-hold protocol has been selected, the port functions of
P2.3, P2.5, and P2.6 cannot be selected without resetting the device. (During the time that the pins
are configured to operate as special-function signals, their special-function values can be read
from the P2_PIN.x bits.) However, the hold function can be dynamically enabled and disabled as
described in “Disabling the Bus-hold Protocol.”
T
HAHAX
HLDA# High to Address No Longer Float
T
HALBZ
HLDA# Low to BHE#, INST, RD#, WR#, WRL#, WRH#
Weakly Driven
T
HAHBV
HLDA# High to BHE#, INST, RD#, WR#, WRL#, WRH# valid
T
CLLH
Clock Falling to ALE Rising; Use to derive other timings.
Table 14-4. HOLD#, HLDA# Timing Definitions (Continued)
Symbol
Parameter
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
Page 567: ......
Page 580: ...Index...
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