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8XC196NT USER’S MANUAL
12-2
12.1.1 Unused Inputs
For predictable performance, it is important to tie unused inputs to V
CC
or V
SS
. Otherwise, they
can float to a mid-voltage level and draw excessive current. Unused interrupt inputs may generate
spurious interrupts if left unconnected.
12.1.2 I/O Port Pin Connections
Tie unused input-only port inputs to V
SS
as shown in Figure 12-1. Chapter 6, “I/O Ports,” contains
information about initializing and configuring the ports. Table 12-2 lists the sections, with page
numbers, that contain the information for each port.
XTAL1
I
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator and the internal clock generators. The internal clock
generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When
using an external clock source instead of the on-chip oscillator, connect the clock
input to XTAL1. The external clock signal must meet the V
IH
specification for XTAL1
(see datasheet).
XTAL2
O
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses
a external clock source instead of the on-chip oscillator.
Table 12-2. I/O Port Configuration Guide
Port
Where to Find Configuration Information
Port 0
“Standard Input-only Port Considerations” on page 6-3
Ports 1 and 2
“Bidirectional Port Pin Configurations” on page 6-9 and “Bidirectional Port Considerations”
on page 6-11
Ports 3 and 4
“Bidirectional Ports 3 and 4 (Address/Data Bus) Operation” on page 6-15
Ports 5 and 6
“Bidirectional Port Pin Configurations” on page 6-9 and “Bidirectional Port Considerations”
on page 6-11
EPORT
“Configuring EPORT Pins” on page 6-24
Table 12-1. Minimum Required Signals(Continued)
Signal
Name
Type
Description
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
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Page 580: ...Index...
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