Intel 8XC196NT, User Manual

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10-15
EVENT PROCESSOR ARRAY (EPA)
The worst-case interrupt latency for a single-interrupt system is 56 state times for external stack
usage and 54 state times for internal stack usage (see “Standard Interrupt Latency” on page 5-9).
To determine the execution time for an interrupt service routine, add up the execution time of the
instructions in the ISR (Table A-9).
The total execution time for the ISR that services interrupts EPA3:0 is 79 state times for external
stack usage or 71 state times for internal stack usage. Therefore, a single capture/compare channel
0–3 can be updated every 125 state times assuming internal stack usage (54 + 71). Each PWM
period requires two updates (one setting and one clearing), so the execution time for a PWM pe-
riod equals 250 state times. At 20 MHz, the PWM period is 25 µs and the maximum PWM fre-
quency is 40 kHz.
The total execution time for the ISR that services the EPAx (capture/compare channels 4–9) in-
terrupt is 175 state times for external stack usage or 159 for internal stack usage. Therefore, a sin-
gle capture/compare channel 4–9 can be updated every 213 state times assuming internal stack
usage (54 + 159). Each PWM period requires two updates (one setting and one clearing), so the
execution time for a PWM period equals 426 state times. At 20 MHz, the PWM period is 42.6 µs
and the maximum PWM frequency is 23.47 kHz.
10.4.2.2 Generating a Medium-speed PWM Output
You can generate a medium-speed, pulse-width modulated output with a single EPA channel and
the PTS set up in PWM toggle mode. “PWM Toggle Mode Example” on page 5-33 describes how
to configure the EPA and PTS. Once started, this method requires no CPU intervention unless you
need to change the output frequency. The method uses a single timer/counter. The timer/counter
is not interrupted during this process, so other EPA channels can also use it if they do not reset it.
The maximum output frequency depends upon the total interrupt latency and interrupt-service ex-
ecution time. As additional EPA channels and the other functions of the microcontroller are used,
the maximum PWM frequency decreases because the total interrupt latency and interrupt-service
execution time increases. To determine the maximum, medium-speed PWM frequency in your
system, calculate your system's worst-case interrupt latency and worst-case interrupt-service ex-
ecution time, and then add them together. The worst-case interrupt latency is the total latency of
all the interrupts (both normal and PTS) used in your system. The worst-case interrupt-service
execution time is the total execution time of all interrupt service routines and PTS cycles.
The following example shows the calculations for a system that uses a single EPA channel, a sin-
gle enabled interrupt, and PTS service. This example assumes that the PTS has been initialized,
the duty cycle and frequency are fixed, and that the interrupt from the capture/compare channel
is not multiplexed (i.e., EPA3:0).