Intel 8XC196NT, User Manual

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8XC196NT USER’S MANUAL
9-6
9.3 HARDWARE CONNECTIONS
Figure 9-3 shows the basic hardware connections for both multiplexed and demultiplexed bus
modes. Table 9-3 lists the interconnections. Note that the shared memory mode supports only a
multiplexed bus, while the standard slave mode supports either a multiplexed or a demultiplexed
bus.
When using a multiplexed bus, connect the master’s AD1 pin to the slave’s SLP1 pin and the mas-
ter’s ALE pin to the slave’s P5.0 pin. When using a demultiplexed bus, connect the master’s ad-
dress output (A1) to the slave’s SLPALE (P5.0) pin. The master’s AD1 (with a multiplexed bus)
or A1 (with a demultiplexed bus) signal must be held high to either write to the slave’s command
register (SLP_CMD) or read the slave’s status register (SLP_STAT). It must be held low to either
write to the slave’s P3_PIN register or read the slave’s P3_REG register.
The configurations shown in Figure 9-3 allow the master to select the slave device by forcing
SLPCS# low. The master can then request that the slave perform a read or a write operation by
forcing SLPRD# or SLPWR# low, respectively. Data is latched on the rising edge of either
SLPRD# or SLPWR#. When the slave completes a read or a write, it notifies the master via the
SLPINT signal.
When the master writes to the P3_PIN register, the input buffer empty (IBE) flag is cleared and
SLPINT is pulled low. When the slave reads P3_PIN, the IBE flag is set and SLPINT is forced
high. This notifies the master that the write operation is completed and another write can be per-
formed.
When the slave writes to P3_REG, the output buffer full (OBF) flag is set and SLPINT is forced
high. This notifies the master that P3_REG contains valid data from the previous read cycle. Note
that this is a pipelined read. The address specified in the previous read cycle is fetched and placed
into the P3_REG register to be read by the master in the next read cycle. When the master reads
from P3_REG, the OBF flag is cleared and SLPINT is pulled low.
Table 9-3. Master and Slave Interconnections
Multiplexed Bus Demultiplexed Bus
Master Slave Master Slave
AD7:0 SLP7:0 D7:0 SLP7:0
ALE SLPALE A1 SLPALE
RD# SLPRD# RD# SLPRD#
WR# SLPWR# WR# SLPWR#
Latched addr. or port pin SLPCS# Latched addr. pin SLPCS#
Interrupt input or port pin SLPINT Interrupt input or port pin SLPINT