Intel 8XC196NT, User Manual

Page: 123 / 597

8XC196NT USER’S MANUAL
5-18
5.6 INITIALIZING THE PTS CONTROL BLOCKS
Each PTS interrupt requires a block of data, in register RAM, called the PTS control block
(PTSCB). The PTSCB identifies which PTS microcode routine will be invoked and sets up the
specific parameters for the routine. You must set up the PTSCB for each interrupt source before
enabling the corresponding PTS interrupts.
The address of the first (lowest) PTSCB byte is stored in the PTS vector table in special-purpose
memory (see “Special-purpose Memory” on page 4-6). Figure 5-9 shows the PTSCB for each
PTS mode. Unused PTSCB bytes can be used as extra RAM.
NOTE
The PTSCB must be located in the internal register file. The location of the
first byte of the PTSCB must be aligned on a quad-word boundary (an address
evenly divisible by 8). Because the PTS uses 16-bit addressing, it cannot
operate across page boundaries. For example, PTSSRC cannot point to a
location on page 05 while PTSDST points to page 00. Both PTSSRC and
PTSDST will operate from the page defined by EP_REG. Write 00H to
EP_REG to select page 00H (see “Accessing Data” on page 4-24).
INT_PEND1
Address:
Reset State:
0012H
00H
When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7 0
NMI EXTINT — RI TI SSIO1 SSIO0 CBF
Bit
Number
Function
7:6
4:0 Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is
cleared when processing transfers to the corresponding interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt Standard Vector
NMI Nonmaskable Interrupt FF203EH
EXTINT EXTINT pin FF203CH
RI SIO Receive FF2038H
TI SIO Transmit FF2036H
SSIO1 SSIO 1 Transfer FF2034H
SSIO0 SSIO 0 Transfer FF2032H
CBF Slave Port Command Buffer Full FF2030H
5 Reserved. This bit is undefined.
Figure 5-8. Interrupt Pending 1 (INT_PEND1) Register