Intel 8XC196NT, User Manual

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14-23
INTERFACING WITH EXTERNAL MEMORY
If the device is reset while in hold, bus contention can occur. For example, a CPU-only device
(80C196NT) would try to fetch the chip configuration byte from external memory after RESET#
was brought high. Bus contention would occur because both the external device and the micro
controller would attempt to access memory. One solution is to use the RESET# signal as the sys-
tem reset; then all bus masters (including the device) are reset at once. Chapter 12, “Minimum
Hardware Considerations,” shows system reset circuit examples.
14.7 BUS-CONTROL MODES
The ALE and WR bits (CCR0.3 and CCR0.2) define which bus-control signals will be generated
during external read and write cycles. Table 14-6 lists the four bus-control modes and shows the
CCR0.3 and CCR0.2 settings for each.
.
14.7.1 Standard Bus-control Mode
In the standard bus-control mode, the device generates the standard bus-control signals: ALE,
RD#, WR#, and BHE# (see Figure 14-10). ALE is asserted while the address is driven, and it can
be used to latch the address externally. RD# is asserted for every external memory read, and WR#
is asserted for every external memory write. When asserted, BHE# selects the bank of memory
that is addressed by the high byte of the data bus.
Table 14-6. Bus-control Mode
Bus-control Mode Bus-control Signals
CCR0.3
(ALE)
CCR0.2
(WR)
Standard Bus-control Mode ALE, RD#, WR#, BHE# 1 1
Write Strobe Mode ALE, RD#, WRL#, WRH# 1 0
Address Valid Strobe Mode ADV#, RD#, WR#, BHE# 0 1
Address Valid with Write Strobe Mode ADV#, RD#, WRL#, WRH# 0 0