Intel 8XC196NT, User Manual

Page: 122 / 597

5-17
STANDARD AND PTS INTERRUPTS
INT_PEND
Address:
Reset State:
0009H
00H
When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7 0
IBF OBE AD EPA0 EPA1 EPA2 EPA3 EPA
x
Bit
Number
Function
7:0 Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is
cleared when processing transfers to the corresponding interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt Standard Vector
IBF Slave Port Input Buffer Full FF200EH
OBE Slave Port Output Buffer Empty FF200CH
AD A/D Conversion Complete FF200AH
EPA0 EPA Capture/Compare Channel 0 FF2008H
EPA1 EPA Capture/Compare Channel 1 FF2006H
EPA2 EPA Capture/Compare Channel 2 FF2004H
EPA3 EPA Capture/Compare Channel 3 FF2002H
EPA x † Multiplexed EPA FF2000H
† EPA 4–9 capture/compare channel events, EPA 0–1 compare channel events, EPA 0–9
capture/compare overruns, and timer overflows can generate this multiplexed interrupt.
The EPA mask and pending registers decode the EPA
x interrupt. Write the EPA mask
registers to enable the interrupt sources; read the EPA pending registers to determine
which source caused the interrupt.
Figure 5-7. Interrupt Pending (INT_PEND) Register