Intel 8XC196NT, User Manual

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Index-15
INDEX
programming, 15-6–15-7
USFR, 15-7
V
V
CC
, 12-1, B-12
and programming modes, 15-14
V
PP
, 12-1, 13-2, 15-13, B-12
and programming modes, 15-14
hardware considerations, 13-7
idle, powerdown, reset status, B-15
V
REF
, 11-5, 12-1, B-12
V
SS
, 12-1, B-12
and programming modes, 15-14
W
Wait states, 14-17–14-19
controlling, 14-17
Watchdog timer, 2-10, 3-14, 12-9, 12-12
and idle mode, 13-4
WDE bit, 12-12
Window selection register‚ See WSR
Windows, 4-1, 4-15–4-22
addressing, 4-19
and addressing modes, 4-22
and memory-mapped SFRs, 4-18
base address, 4-17, 4-19
examples, 4-19–4-22
nonwindowable locations, 4-18, 4-20
selecting, 4-16
setting up with linker loader, 4-20
table of, 4-16, 4-17, 4-18, C-66
WORD, defined, 3-3
World Wide Web, 1-10
WR#, 14-5, B-13
during bus hold, 14-19
idle, powerdown, reset status, B-14
Wraparound, defined, 4-2
WRH#, 14-3, 14-5, B-13
Write-strobe mode timing, 14-27
WRL#, 14-5, B-13
WSR, 4-16, 14-22
X
X, defined, 1-5
x, defined, 1-4
XCH instruction, A-2, A-3, A-44, A-46, A-55,
A-62
XCHB instruction, A-2, A-3, A-44, A-46, A-55,
A-62
XOR instruction, A-2, A-45, A-48, A-53, A-60
XORB instruction, A-2, A-45, A-48, A-49, A-53,
A-60
XTAL1, 12-2, B-13
and Miller effect, 12-8
and programming modes, 15-13, 15-31
and SIO baud rate, 7-11
and SSIO baud rate, 8-10
hardware connections, 12-6, 12-7
idle, powerdown, reset status, B-15
XTAL2, 12-2, B-13
and programming modes, 15-31
hardware connections, 12-6, 12-7
idle, powerdown, reset status, B-15
Y
y, defined, 1-4
Z
Zero (Z) flag, A-4, A-5, A-22, A-23, A-24, A-25,
C-44