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14-1
CHAPTER 14
INTERFACING WITH EXTERNAL MEMORY
The device can interface with a variety of external memory devices. It supports either a fixed 8-
bit bus width, a fixed 16-bit bus width, or a dynamic 8-bit/16-bit bus width; internal control of
wait states for slow external memory devices; a bus-hold protocol that enables external devices
to take over the bus; and several bus-control modes. These features provide a great deal of flexi-
bility when interfacing with external memory devices.
In addition to describing the signals and registers related to external memory, this chapter discuss-
es the process of fetching the chip configuration bytes and configuring the external bus. It also
provides examples of external memory configurations.
14.1 INTERNAL AND EXTERNAL ADDRESSES
The address that external devices see is different from the address that the device generates inter-
nally. Internally, the device has 24 address lines, but only the lower 20 address lines (A19:16 and
AD15:0) are implemented with external pins. The absence of the upper four address bits at the
external pins causes different internal addresses to have the same external address. For example,
the internal addresses FF2080H, 7F2080H, and F2080H all appear at the 20 external pins as
F2080H. The upper nibble of the internal address has no effect on the external address.
The address seen by an external device also depends on the number of address lines that the ex-
ternal system uses. If the address on the external pins (A19:16 and AD15:0) is F2080H, and only
A17:16 and AD15:0 are connected to the external device, the external device sees 32080H. The
upper four address lines A19:16 are implemented by the EPORT. Table 14-1 shows how the ex-
ternal address depends on the number of EPORT lines used to address the external device.
Table 14-1. Example of Internal and External Addresses
EPORT Lines
Connected to the
External Device
Internal Address
Address on the
Device Pins
Address Seen by
External Device
A16
x
F2080H
F2080H
12080H
A17:16
x
F2080H
F2080H
32080H
A18:16
x
F2080H
F2080H
72080H
A19:16
x
F2080H
F2080H
F2080H
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
Page 567: ......
Page 580: ...Index...
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