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11-5
ANALOG-TO-DIGITAL CONVERTER
11.4.1 Programming the A/D Test Register
The AD_TEST register (Figure 11-2) selects either an analog input or a test voltage (ANGND or
V
REF
) for conversion and specifies an offset voltage to be applied to the resistor ladder. To use the
zero-offset adjustment, first perform two conversions, one on ANGND and one on V
REF
. With the
results of these conversions, use a software routine to calculate the zero-offset error. Specify the
zero-offset adjustment by writing the appropriate value to AD_TEST. This offset voltage is added
to the resistor ladder and applies to all input channels. “Understanding A/D Conversion Errors”
on page 11-14 describes zero-offset and other errors inherent in A/D conversions.
AD_TEST
Address:
Reset State:
1FAEH
C0H
The A/D test (AD_TEST) register enables conversions on ANGND and V
REF
and specifies
adjustments for DC offset errors. Its functions allow you to perform two conversions, one on ANGND
and one on V
REF
. With these results, a software routine can calculate the offset and gain errors.
7
0
—
—
—
—
OFF1
OFF0
TV
TE
Bit
Number
Bit
Mnemonic
Function
7:4
—
Reserved; for compatibility with future devices, write zeros to these bits.
3:2
OFF1:0
Offset
These bits allows you to set the zero-offset point.
OFF1 OFF0
0
0
no adjustment
0
1
add 2.5 mV
1
0
subtract 2.5 mV
1
1
subtract 5.0 mV
1
TV
Test Voltage
This bit selects the test voltage for a test mode conversion. (The TE bit
must be set to enable test mode.)
1 = V
REF
0 = ANGND
0
TE
Test Enable
This bit determines whether normal or test mode conversions will be
performed. A normal conversion converts the analog signal input on one
of the analog input channels. A test conversion allows you to perform a
conversion on ANGND or V
REF
, selected by the TV bit.
1 = test
0 = normal
Figure 11-2. A/D Test (AD_TEST) Register
Summary of Contents for 8XC196NT
Page 1: ...8XC196NT Microcontroller User s Manual...
Page 2: ...8XC196NT Microcontroller User s Manual June 1995 Order Number 272317 003...
Page 22: ...1 Guide to This Manual...
Page 23: ......
Page 35: ......
Page 36: ...2 Architectural Overview...
Page 37: ......
Page 49: ......
Page 50: ...3 Programming Considerations...
Page 51: ......
Page 66: ...4 Memory Partitions...
Page 67: ......
Page 104: ...5 Standard and PTS Interrupts...
Page 105: ......
Page 147: ......
Page 148: ...6 I O Ports...
Page 149: ......
Page 176: ...7 Serial I O SIO Port...
Page 177: ......
Page 194: ...8 Synchronous Serial I O SSIO Port...
Page 195: ......
Page 211: ......
Page 212: ...9 Slave Port...
Page 213: ......
Page 231: ......
Page 232: ...10 Event Processor Array EPA...
Page 233: ......
Page 270: ...11 Analog to digital Converter...
Page 271: ......
Page 291: ......
Page 292: ...12 Minimum Hardware Considerations...
Page 293: ......
Page 306: ...13 Special Operating Modes...
Page 307: ......
Page 317: ......
Page 318: ...14 Interfacing with External Memory...
Page 319: ......
Page 362: ...15 Programming the Nonvolatile Memory...
Page 363: ......
Page 408: ...A Instruction Set Reference...
Page 409: ......
Page 476: ...B Signal Descriptions...
Page 477: ......
Page 493: ......
Page 494: ...C Registers...
Page 495: ......
Page 565: ......
Page 566: ...Glossary...
Page 567: ......
Page 580: ...Index...
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Page 597: ......