Intel 8XC196NT, User Manual

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15-3
PROGRAMMING THE NONVOLATILE MEMORY
15.3 SECURITY FEATURES
Several security features enable you to control access to both internal and external memory. Read
and write protection bits in the chip configuration register (CCR0), combined with a security key,
allow various levels of internal memory protection. Two UPROM bits disable fetches of instruc-
tions and data from external memory. An additional bit enables circuitry that can detect an oscil-
lator failure and cause a device reset. (See Figure 15-1 on page 15-7 for more information.)
15.3.1 Controlling Access to Internal Memory
The lock bits in the chip configuration register (CCR0) control access to the OTPROM. The reset
sequence loads the CCRs from the CCBs for normal operation and from the PCCBs when enter-
ing programming modes. You can program the CCBs using any of the programming methods, but
only slave programming mode allows you to program the PCCBs.
NOTE
The developers have made a substantial effort to provide an adequate program
protection scheme. However, Intel cannot and does not guarantee that these
protection methods will always prevent unauthorized access.
FF203F
FF2030
Upper interrupt vectors
FF202F
FF2020
Security key
FF201F Reserved (must contain 20H)
FF201E Reserved (must contain FFH)
FF201D Reserved (must contain 20H)
FF201C CCB2
FF201B Reserved (must contain 20H)
FF201A CCB1
FF2019 Reserved (must contain 20H)
FF2018 CCB0
FF2017
FF2016
OFD flag for QROM or MROM codes
†
FF2015
FF2014
Reserved (each location must contain FFH)
FF2013
FF2000
Lower interrupt vectors
Table 15-1. 87C196NT OTPROM Memory Map (Continued)
Address
Range
(Hex)
Description
†
Intel manufacturing uses this location to determine whether to program the OFD bit.
Customers with QROM or MROM codes who desire oscillator failure detection should
equate this location to the value 0CDEH.