Freescale Semiconductor MC9S12ZVM series, Reference Manual

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Chapter 2 Port Integration Module (S12ZVMPIMV1)
MC9S12ZVM Family Reference Manual Rev. 1.3
106 Freescale Semiconductor
This is a generic description of the standard port interrupt enable registers. Refer to Table 2-22 to
determine the implemented bits in the respective register. Unimplemented bits read zero.
2.3.3.7 Port Interrupt Flag Register
This is a generic description of the standard port interrupt flag registers. Refer to Table 2-22 to determine
the implemented bits in the respective register. Unimplemented bits read zero.
Table 2-14. Port Interrupt Enable Register Field Descriptions
Field Description
7-0
PIEx7-0
Port Interrupt Enable — Activate pin interrupt (KWU)
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
Address 0x028E PIFADH
0x028F PIFADL
0x02D7 PIFS
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime, write 1 to clear
7 6 5 4 3 2 1 0
R
PIFx7 PIFx6 PIFx5 PIFx4 PIFx3 PIFx2 PIFx1 PIFx0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-16. Port Interrupt Flag Register
Table 2-15. Port Interrupt Flag Register Field Descriptions
Field Description
7-0
PIFx7-0
Port Interrupt Flag — Signal pin event (KWU)
This flag asserts after a valid active edge was detected on the related pin (see Section 2.4.5, “Pin interrupts and Key-
Wakeup (KWU) ”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt
will occur if the associated interrupt enable bit is set.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred
0 No active edge occurred