Freescale Semiconductor MC9S12ZVM series, Reference Manual

Page: 786 / 825

Appendix H SPI Electrical Specifications
MC9S12ZVM Family Reference Manual Rev. 1.3
786 Freescale Semiconductor
In Figure H-6. the timing diagram for slave mode with transmission format CPHA=1 is depicted.
Figure H-6. SPI Slave Timing (CPHA=1)
Table H-2. SPI Slave Mode Timing Characteristics -40
°
C to 175
°
C
Num C Characteristic Symbol Unit
Min Typ Max
1 D SCK Frequency f
sck
DC — 1
/
4
(1)
1. f
bus
max is 40MHz at temperatures above 150
°
C
f
bus
1 D SCK Period t
sck
4 — t
bus
2 D Enable Lead Time t
lead
4 — — t
bus
3 D Enable Lag Time t
lag
4 — — t
bus
4 D Clock (SCK) High or Low Time t
wsck
2t
bus
-
(t
rfi
+ t
rfo)
— — ns
5 D Data Setup Time (Inputs) t
su
3 — — ns
6 D Data Hold Time (Inputs) t
hi
2 — — ns
7 D Slave Access Time (time to data active) t
a
— — 28 ns
8 D Slave MISO Disable Time t
dis
— — 26 ns
9a D Data Valid after SCK Edge (-40
°
C < T
j
< 150
°
C) t
vsck
— —
(2)
2. 0.5t
bus
added due to internal synchronization delay
ns
9b D Data Valid after SCK Edge (150
°
C <T
j
< 175
°
C)
(1)
t
vsck
— —
(2)
ns
10a D Data Valid after SS fall (-40
°
C < T
j
< 150
°
C) t
vss
— —
(2)
ns
10b D Data Valid after SS fall (150
°
C < T
j
< 175
°
C)
(1)
t
vss
— —
(2)
ns
11 D Data Hold Time (Outputs) t
ho
22 — — ns
12 D Rise and Fall Time Inputs t
rfi
— — 8 ns
13 D Rise and Fall Time Outputs t
rfo
— — 8 ns
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
1
5 6
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
4 4
9
12 13
11
(CPOL
=
0)
(CPOL
=
1)
SS
(INPUT)
2
12 13
3
NOTE: Not defined!
SLAVE
7
8
see
note
∞
23 0.5 t
bus
⋅
+
25 0.5 t
bus
⋅
+
23 0.5 t
bus
⋅
+
25 0.5 t
bus
⋅
+