Freescale Semiconductor MC9S12ZVM series, Reference Manual

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Appendix C ADC Electrical Specifications
MC9S12ZVM Family Reference Manual Rev. 1.2
Freescale Semiconductor 763
Appendix C
ADC Electrical Specifications
This section describes the characteristics of the analog-to-digital converter.
C.1 ADC Operating Characteristics
The Table C-1 shows conditions under which the ADC operates.
The following constraints exist to obtain full-scale, full range results:
V
SSA
≤
V
RL
≤
V
IN
≤
V
RH
≤
V
DDA
.
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table C-1. ADC Operating Characteristics
C.1.1 Factors Influencing Accuracy
Source resistance, source capacitance and current injection have an influence on the accuracy of the ADC
.
Figure C-1.
A further factor is that PortAD pins that are configured as output drivers switching.
Supply voltage 4.5 V < V
DDA
< 5.5 V, Junction Temperature From –40
o
C To +175
o
C
Num C Rating Symbol Min Typ Max Unit
1 D Reference potential
Low
High V
RL
V
RH
V
SSA
V
DDA
/2
—
— V
DDA
/2
V
DDA
V
V
2 D Voltage difference V
DDX
to V
DDA
∆
VDDX
-0.1 0 0.1 V
3 D Voltage difference V
SSX
to V
SSA
∆
VSSX
–0.1 0 0.1 V
4 C Differential reference voltage
(1)
1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V
V
RH
-V
RL
3.13 5.0 5.5 V
5 C ADC Clock Frequency (derived from bus clock via the
prescaler).
f
ATDCLK
0.25 — 8.33 MHz
6 D Buffer amplifier turn on time (delay after module
start/recovery from Stop mode)
t
REC
— — 1
µ
s
7 D ADC disable time t
DISABLE
— — 3 bus
clock
cycles
8 D
ADC Conversion Period
(2)
12 bit resolution:
10 bit resolution:
8 bit resolution:
2. The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock
cycles.
N
CONV12
N
CONV10
N
CONV8
19
18
16 —
—
— 39
38
36 ADC
clock
cycles