Freescale Semiconductor MC9S12ZVM series, Reference Manual

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Chapter 14 Pulse Width Modulator with Fault Protection (PMF15B6CV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
538 Freescale Semiconductor
Figure 14-62. Asymmetric Waveform - Phase Shift PWM Output
14.4.8 Variable Edge Placement PWM Output
In complementary edge-aligned mode, the timing of both edges of the PWM output can be controlled using
the PEC
x bits in the PMFICCTL register and the CINV n bits in the PMFCINV register.
The edge-aligned signal created by the even value register and the associated CINV n bit is ANDed with
the signal created by the odd value register and its associated CINV n bit. The resulting signal can
optionally be negated by PINV x and is then fed into the complement and deadtime logic ( Figure 14-63 ).
If the value of the inverted register exceeds the non-inverted register value, no output pulse is generated
(0% or 100% duty cycle). See right half of
Figure 14-64 .
In contrast to asymmetric PWM output mode, the PWM phase shift can pass the PWM cycle boundary.
Figure 14-63. Logic AND Function with Signal Inversions
Modulus = 4
0
1
2
3
4
Up/Down Counter
Even PWM
Value = 1
Odd PWM
Value = 3
Even PWM
Value = 3
Odd PWM
Value = 1
Even PWM
Value
Odd PWM
Value
Odd PWM
Value
Even PWM
Value
PINVA
PWM
GENERATOR 1
PWM
GENERATOR 0
CINV0
CINV1
PECA=1
to complement
COMPSRC
logic and
dead time
insertion