Freescale Semiconductor MC9S12ZVM series, Reference Manual

Page: 534 / 825

Chapter 14 Pulse Width Modulator with Fault Protection (PMF15B6CV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
534 Freescale Semiconductor
NOTE
IPOL x bits are buffered so only one PWM register is used per PWM cycle.
If an IPOL x bit changes during a PWM period, the new value does not take
effect until the next PWM period.
IPOL x bits take effect at the end of each PWM cycle regardless of the state
of the related LDOK bit or global load OK.
Figure 14-55. Internal Correction Logic when ISENS = 01
To detect the current status, the voltage on each IS input is sampled twice in a PWM period, at the end of
each deadtime. The value is stored in the DT
n bits in the PMF Deadtime Sample register (PMFDTMS).
The DT n bits are a timing marker especially indicating when to toggle between PWM value registers.
Software can then set the IPOL x bit to toggle PMFVAL registers according to DT n values.
Figure 14-56. Current Status Sense Scheme for Deadtime Correction
Both D flip-flops latch low, DT0 = 0, DT1 = 0, during deadtime periods if current is large and flowing out
of the complementary circuit. See
Figure 14-56 . Both D flip-flops latch the high, DT0 = 1, DT1 = 1, during
deadtime periods if current is also large and flowing into the complementary circuit.
However, under low-current, the output voltage of the complementary circuit during deadtime is
somewhere between the high and low levels. The current cannot free-wheel through the opposition anti-
body diode, regardless of polarity, giving additional distortion when the current crosses zero.
DEADTIME
GENERATOR
D Q
CLK
IPOL x BIT
A/B
A
B
TOP PWM
BOTTOM PWM
PWM CYCLE START
PWM CONTROLLED
BY ODD PMFVAL REGISTER
PWM CONTROLLED
BY EVEN PMFVAL REGISTER
PWM0
PWM1
D Q
CLK
D Q
CLK
VOLTAGE
SENSOR
IS0 PIN
PWM0
PWM1
DT0
DT1
POSITIVE
CURRENT
NEGATIVE
CURRENT