Chapter 9 Analog-to-Digital Converter (ADC12B_LBA_V1)
MC9S12ZVM Family Reference Manual Rev. 1.3
350
Freescale Semiconductor
9.5
Functional Description
9.5.1
Overview
The ADC12B_LBA consists of an analog sub-block and a digital sub-block. It is a successive
approximation analog-to-digital converter including a sample-and-hold mechanism and an internal charge
scaled C-DAC (switched capacitor scaled digital-to-analog converter) with a comparator to realize the
successive approximation algorithm.
9.5.2
Analog Sub-Block
The analog sub-block contains all analog circuits (sample and hold, C-DAC, analog Comparator, and so
on) required to perform a single conversion. Separate power supplies VDDA and VSSA allow noise from
the MCU circuitry to be isolated from the analog sub-block for improved accuracy.
9.5.2.1
Analog Input Multiplexer
The analog input multiplexers connect one of the external or internal analog input channels to the sample
and hold storage node.
9.5.2.2
Sample and Hold Machine with Sample Buffer Amplifier
The Sample and Hold Machine controls the storage and charge of the storage node (sample capacitor) to
the voltage level of the analog signal at the selected ADC input channel. This architecture employs the
advantage of reduced crosstalk between channels.
The sample buffer amplifier is used to raise the effective input impedance of the A/D machine, so that
external components (higher bandwidth or higher impedance connected as specified) are less significant
to accuracy degradation.
During the sample phase, the analog input connects first via a sample buffer amplifier with the storage node
always for two ADC clock cycles (“Buffer” sample time). For the remaining sample time (“Final” sample
time) the storage node is directly connected to the analog input source. Please see also
illustration and the Appendix of the device reference manual for more details.
The input analog signals are unipolar and must be within the potential range of VSSA to VDDA.
During the hold process, the analog input is disconnected from the storage node.
Figure 9-28. Sampling and Conversion Timing Example (8-bit Resolution, 4 Cycle Sampling)
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"Buffer"
Sample Time
(2 cycles)
"Final"
Sample Time
(N - 2 cycles)
Total Sample Time
(N = SMP[4:0])
SAR Sequence
(Resolution Dependent Length: SRES[2:0])
Sample CAP hold phase
ADC_CLK
