Chapter 12 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
435
12.3.3.2
Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
The number of bytes to be transmitted or received is determined by the data length code in the
corresponding DLR register.
Module Base + 0x00X2
7
6
5
4
3
2
1
0
R
W
Reset:
x
x
x
x
x
x
x
x
= Unused; always read ‘x’
Figure 12-32. Identifier Register 2 — Standard Mapping
Module Base + 0x00X3
7
6
5
4
3
2
1
0
R
W
Reset:
x
x
x
x
x
x
x
x
= Unused; always read ‘x’
Figure 12-33. Identifier Register 3 — Standard Mapping
Module Base + 0x00X4 to Module Base + 0x00XB
7
6
5
4
3
2
1
0
R
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
Reset:
x
x
x
x
x
x
x
x
Figure 12-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
Table 12-32. DSR0–DSR7 Register Field Descriptions
Field
Description
7-0
DB[7:0]
Data bits 7-0
