Chapter 12 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
427
12.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”
To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Table 12-21. CANIDAR0–CANIDAR3 Register Field Descriptions
Field
Description
7-0
AC[7:0]
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
Module Base + 0x0018 to Module Base + 0x001B
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
7
6
5
4
3
2
1
0
R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
W
Reset
0
0
0
0
0
0
0
0
Figure 12-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Table 12-22. CANIDAR4–CANIDAR7 Register Field Descriptions
Field
Description
7-0
AC[7:0]
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
Module Base + 0x0014 to Module Base + 0x0017
Access: User read/write
(1)
7
6
5
4
3
2
1
0
R
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
W
Reset
0
0
0
0
0
0
0
0
Figure 12-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
