Chapter 4 Interrupt (S12ZINTV0)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
137
Read: Anytime
Write: Anytime
Address: 0x00001E
7
6
5
4
3
2
1
0
R
0
0
0
0
0
PRIOLVL[2:0]
W
Reset
0
0
0
0
0
0
0
1
(1)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
= Unimplemented or Reserved
Figure 4-11. Interrupt Request Configuration Data Register 6 (INT_CFDATA6)
Address: 0x00001F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
PRIOLVL[2:0]
W
Reset
0
0
0
0
0
0
0
1
(1)
1. Please refer to the notes following the PRIOLVL[2:0] description below.
= Unimplemented or Reserved
Figure 4-12. Interrupt Request Configuration Data Register 7 (INT_CFDATA7)
Table 4-6. INT_CFDATA0–7 Field Descriptions
Field
Description
2–0
PRIOLVL[2:0]
Interrupt Request Priority Level Bits — The PRIOLVL[2:0] bits configure the interrupt request priority level of
the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level (“1”).
Please also refer to
for available interrupt request priority levels.
Note: Write accesses to configuration data registers of unused interrupt channels are ignored and read
accesses return all 0s. For information about what interrupt channels are used in a specific MCU, please
refer to the Device Reference Manual for that MCU.
Note: When non I-bit maskable request vectors are selected, writes to the corresponding INT_CFDATA
registers are ignored and read accesses return all 0s. The corresponding vectors do not have
configuration data registers associated with them.
Note: Write accesses to the configuration register for the spurious interrupt vector request
(vector base + 0x0001DC) are ignored and read accesses return 0x07 (request is handled by the CPU,
PRIOLVL = 7).
Table 4-7. Interrupt Priority Levels
Priority
PRIOLVL2
PRIOLVL1
PRIOLVL0
Meaning
0
0
0
Interrupt request is disabled
low
0
0
1
Priority level 1
0
1
0
Priority level 2
0
1
1
Priority level 3
1
0
0
Priority level 4
