Chapter 5 Background Debug Controller (S12ZBDCV2)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
165
after the memory read was performed. If enabled, an ACK pulse is driven before the data bytes are
transmitted.
The examples show the READ_MEM.B{_WS}, READ_MEM.W{_WS} and READ_MEM.L{_WS}
commands.
5.4.4.12
READ_DBGTB
This command is only available on devices, where the DBG module includes a trace buffer. Attempted use
of this command on devices without a traace buffer return 0x00.
Read 64 bits from the DBG trace buffer. Refer to the DBG module description for more detailed
information. If enabled an ACK pulse is generated before each 32-bit longword is ready to be read by the
host. After issuing the first ACK a timeout is still possible whilst accessing the second 32-bit longword,
since this requires separate internal accesses. The first 32-bit longword corresponds to trace buffer line
bits[31:0]; the second to trace buffer line bits[63:32]. If ACK handshaking is disabled, the host must wait
16 clock cycles (DLY) after completing the first 32-bit read before starting the second 32-bit read.
5.4.4.13
READ_SAME.sz, READ_SAME.sz_WS
Read DBG trace buffer
Non-intrusive
0x07
TB Line [31-
24]
TB Line [23-
16]
TB Line [15-
8]
TB Line [7-
0]
TB Line [63-
56]
TB Line [55-
48]
TB Line [47-
40]
TB Line [39-
32]
host
→
target
D
A
C
K
target
→
host
target
→
host
target
→
host
target
→
host
D
A
C
K
target
→
host
target
→
host
target
→
host
target
→
host
READ_SAME
Read same location specified by previous READ_MEM{_WS}
Non-intrusive
0x54
Data[15-8]
Data[7-0]
host
→
target
D
A
C
K
target
→
host
target
→
host
READ_SAME_WS
Read same location specified by previous READ_MEM{_WS}
Non-intrusive
0x55
BDCCSRL
Data [15-8]
Data [7-0]
host
→
target
D
L
Y
target
→
host
target
→
host
target
→
host
