Chapter 9 Analog-to-Digital Converter (ADC12B_LBA_V1)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
325
Table 9-9. ADCFLWCTL Field Descriptions
Field
Description
7
SEQA
Conversion Sequence Abort Event — This bit indicates that a conversion sequence abort event is in progress.
When this bit is set the ongoing conversion sequence and current CSL will be aborted at the next conversion
boundary. This bit gets cleared when the ongoing conversion sequence is aborted and ADC is idle.
This bit can only be set if bit ADC_EN is set.
This bit is cleared if bit ADC_EN is clear.
Data Bus Control:
This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0].
Writing a value of 1’b0 does not clear the flag.
Writing a one to this bit does not clear it but causes an overrun if the bit has already been set. See
for more
details.
Internal Interface Control:
This bit can be controlled via the internal interface Signal “Seq_Abort” if access control is configured accordingly
via ACC_CFG[1:0]. After being set an additional request via the internal interface Signal “Seq_Abort” causes an
overrun. See also conversion flow control in case of overrun situations.
General:
In both conversion flow control modes (Restart Mode and Trigger Mode) when bit RSTA gets set automatically
bit SEQA gets set when the ADC has not reached one of the following scenarios:
- A Sequence Abort request is about to be executed or has been executed.
- “End Of List” command type has been executed or is about to be executed
In case bit SEQA is set automatically the Restart error flag RSTA_EIF is set to indicate an unexpected Restart
Request.
0 No conversion sequence abort request.
1 Conversion sequence abort request.
6
TRIG
Conversion Sequence Trigger Bit — This bit starts a conversion sequence if set and no conversion or
conversion sequence is ongoing. This bit is cleared when the first conversion of a sequence starts to sample.
This bit can only be set if bit ADC_EN is set.
This bit is cleared if bit ADC_EN is clear.
Data Bus Control:
This bit can be controlled via the data bus if access control is configured accordingly via ACC_CFG[1:0].
Writing a value of 1’b0 does not clear the flag.
After being set this bit can not be cleared by writing a value of 1’b1 instead the error flag TRIG_EIF is set. See
also
for
more details.
Internal Interface Control:
This bit can be controlled via the internal interface Signal “Trigger” if access control is configured accordingly via
ACC_CFG[1:0]. After being set an additional request via internal interface Signal “Trigger“ causes the flag
TRIG_EIF to be set.
0 No conversion sequence trigger.
1 Trigger to start conversion sequence.
