![Freescale Semiconductor MC9S12ZVM series Reference Manual Download Page 389](http://html1.mh-extra.com/html/freescale-semiconductor/mc9s12zvm-series/mc9s12zvm-series_reference-manual_2330602389.webp)
Chapter 11 Timer Module (TIM16B4CV3) Block Description
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
389
11.3.2.2
Timer Compare Force Register (CFORC)
Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
11.3.2.3
Timer Count Register (TCNT)
Table 11-2. TIOS Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field
Description
3:0
IOS[3:0]
Input Capture or Output Compare Channel Configuration
0 The corresponding implemented channel acts as an input capture.
1 The corresponding implemented channel acts as an output compare.
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W RESERVED
RESERVED
RESERVED
RESERVED
FOC3
FOC2
FOC1
FOC0
Reset
0
0
0
0
0
0
0
0
Figure 11-5. Timer Compare Force Register (CFORC)
Table 11-3. CFORC Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field
Description
3:0
FOC[3:0]
Note: Force Output Compare Action for Channel 3:0 — A write to this register with the corresponding data
bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action
taken is the same as if a successful comparison had just taken place with the TCx register except the
interrupt flag does not get set. If forced output compare on any channel occurs at the same time as the
successful output compare then forced output compare action will take precedence and interrupt flag won’t
get set.
Module Base + 0x0004
15
14
13
12
11
10
9
9
R
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
TCNT9
TCNT8
W
Reset
0
0
0
0
0
0
0
0
Figure 11-6. Timer Count Register High (TCNTH)