Freescale Semiconductor MC9S12ZVM series, Reference Manual

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Chapter 9 Analog-to-Digital Converter (ADC12B_LBA_V1)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor 341
9.4.2.17 ADC Command Register 2 (ADCCMD_2)
A command which contains reserved bit settings causes the error flag CMD_EIF being set and ADC cease
operation.
Read: Anytime
Write: Only writable if bit SMOD_ACC is set
(see also
Section 9.4.2.2, “ADC Control Register 1 (ADCCTL_1) bit SMOD_ACC description for more
details)
NOTE
If bit SMOD_ACC is set modifying this register must be done carefully -
only when no conversion and conversion sequence is ongoing.
Module Base + 0x0016
15 14 13 12 11 10 9 8
R
SMP[4:0]
0 0
Reserved
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 9-20. ADC Command Register 2 (ADCCMD_2)
Table 9-24. ADCCMD_2 Field Descriptions
Field Description
15-11
SMP[4:0]
Sample Time Select Bits — These four bits select the length of the sample time in units of ADC conversion
clock cycles. Note that the ADC conversion clock period is itself a function of the prescaler value (bits PRS[6:0]).
Table 9-25 lists the available sample time lengths.
Table 9-25. Sample Time Select
SMP[4] SMP[3] SMP[2] SMP[1] SMP[0]
Sample Time
in Number of
ADC Clock Cycles
0 0 0 0 0 4
0 0 0 0 1 5
0 0 0 1 0 6
0 0 0 1 1 7
0 0 1 0 0 8
0 0 1 0 1 9
0 0 1 1 0 10
0 0 1 1 1 11
0 1 0 0 0 12
0 1 0 0 1 13