Chapter 14 Pulse Width Modulator with Fault Protection (PMF15B6CV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
544
Freescale Semiconductor
14.4.12 PWM Generator Loading
14.4.12.1 Load Enable
The load okay bit, LDOK, enables loading the PWM generator with:
•
A prescaler divisor—from the PRSC bits in PMFFQC register
•
A PWM period—from the PWM counter modulus registers
•
A PWM pulse width—from the PWM value registers
LDOK prevents reloading of these PWM parameters before software is finished calculating them. Setting
LDOK allows the prescaler bits, PMFMOD and PMFVAL registers to be loaded into a set of buffers. The
loaded buffers are used by the PWM generator at the beginning of the next PWM reload cycle. Set LDOK
by reading it when it is a logic zero and then writing a logic one to it. After the PWM reload event, LDOK
is automatically cleared.
If LDOK is set in the same cycle as the PWM reload event occurs, then the current buffers will be used
and the LDOK is valid at the next PWM reload event. See
If an asserted LDOK bit is attempted to be set again one cycle prior to the PWM reload event, then the
buffers will loaded and LDOK will be cleared automatically. Else if the write access to the set LDOK bit
occurs in the same cycle with the reload event, the buffers will also be loaded but the LDOK remains valid
also for the next PWM reload event. See
Figure 14-71. Setting cleared LDOK bit at PWM reload event
bus clock
LDOK write
LDOK bit
PWM reload
bus clock
LDOK write
LDOK bit
PWM reload
