Chapter 1 Device Overview MC9S12ZVM-Family
MC9S12ZVM Family Reference Manual Rev. 1.3
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Freescale Semiconductor
1.8.3
Device Level PMF Connectivity
1.8.4
BDC Clock Source Connectivity
The BDC clock, BDCCLK, is mapped to the IRCCLK generated in the CPMU module.
The BDC clock, BDCFCLK is mapped to the device bus clock, generated in the CPMU module.
1.8.5
LINPHY Connectivity
The VLINPHY supply is connected to the device HD pin.
1.8.6
FTMRZ Connectivity
The soc_erase_all_req input to the flash module is driven directly by a BDC erase flash request resulting
from the BDC ERASE_FLASH command.
The FTMRZ FCLKDIV register is forced to 0x05 by the BDC ERASE_FLASH command. This
configures the clock frequency correctly for the initial bus frequency on leaving reset. The bus frequency
must not be changed before launching the ERASE_FLASH command.
1.8.7
CPMU Connectivity
The API clock generated in the CPMU is not mapped to a device pin in the MC9S12ZVM-Family.
Table 1-9. Mapping of PMF signals
PMF Connection
Usage
Channel0
High-Side Gate and Source Pins HG[0], HS[0]
Channel1
Low-Side Gate and Source Pins LG[0], LS[0]
Channel2
High-Side Gate and Source Pins HG[1], HS[1]
Channel3
Low-Side Gate and Source Pins LG[1], LS[1]
Channel4
High-Side Gate and Source Pins HG[2], HS[2]
Channel5
Low-Side Gate and Source Pins LG[2], LS[2]
FAULT5
External FAULT5 pin
FAULT4
HD Over voltage or GDU over current
FAULT3
VLS under voltage
FAULT2
GDU Desaturation[2] or GDU over current
FAULT1
GDU Desaturation[1] or GDU over current
FAULT0
GDU Desaturation[0] or GDU over current
IS2
GDU Phase Status[2]
IS1
GDU Phase Status[1]
IS0
GDU Phase Status[0]
async_event_edge_sel[1:0]
Tied to b11 (both edges active)
