Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6)
MC9S12ZVM Family Reference Manual Rev. 1.3
282
Freescale Semiconductor
8.3.2.20
High Temperature Trimming Register (CPMUHTTR)
The CPMUHTTR register configures the trimming of the S12CPMU_UHV_V6 temperature sense.
Read: Anytime
Write: Anytime
Module Base + 0x0017
7
6
5
4
3
2
1
0
R
HTOE
0
0
0
HTTR3
HTTR2
HTTR1
HTTR0
W
Reset
0
0
0
0
F
F
F
F
After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for
details.
= Unimplemented or Reserved
Figure 8-26. High Temperature Trimming Register (CPMUHTTR)
Table 8-24. CPMUHTTR Field Descriptions
Field
Description
7
HTOE
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled.
0 The temperature sense offset is disabled. HTTR[3:0] bits don’t care.
1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset.
3–0
HTTR[3:0]
High Temperature Trimming Bits — See
for trimming effects.
Table 8-25. Trimming Effect of HTTR
Bit
Trimming Effect
HTTR[3]
Increases V
HT
twice of HTTR[2]
HTTR[2]
Increases V
HT
twice of HTTR[1]
HTTR[1]
Increases V
HT
twice of HTTR[0]
HTTR[0]
Increases V
HT
(to compensate Temperature Offset)
