Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6)
MC9S12ZVM Family Reference Manual Rev. 1.3
244
Freescale Semiconductor
8.1.1
Features
The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output
amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
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Supports crystals or resonators from 4MHz to 20MHz.
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High noise immunity due to input hysteresis and spike filtering.
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Low RF emissions with peak-to-peak swing limited dynamically
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Transconductance (gm) sized for optimum start-up margin for typical crystals
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Dynamic gain control eliminates the need for external current limiting resistor
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Integrated resistor eliminates the need for external bias resistor
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Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits
power
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Optional oscillator clock monitor reset
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Optional full swing mode for higher immunity against noise injection on the cost of higher power
consumption and increased emission
The Voltage Regulator (VREGAUTO) has the following features:
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Input voltage range from 6 to 18V (nominal operating range)
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Low-voltage detect (LVD) with low-voltage interrupt (LVI)
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Power-on reset (POR)
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Low-voltage reset (LVR)
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On Chip Temperature Sensor and Bandgap Voltage measurement via internal ADC channel.
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Voltage Regulator providing Full Performance Mode (FPM) and Reduced Performance Mode
(RPM)
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External ballast device support to reduce internal power dissipation
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Capable of supplying both the MCU internally plus external components
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Over-temperature interrupt
The Phase Locked Loop (PLL) has the following features:
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Highly accurate and phase locked frequency multiplier
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Configurable internal filter for best stability and lock time
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Frequency modulation for defined jitter and reduced emission
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Automatic frequency lock detector
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Interrupt request on entry or exit from locked condition
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PLL clock monitor reset
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Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based.
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PLL stability is sufficient for LIN communication in slave mode, even if using IRC1M as reference
clock
The Internal Reference Clock (IRC1M) has the following features:
