Chapter 1 Device Overview MC9S12ZVM-Family
MC9S12ZVM Family Reference Manual Rev. 1.3
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Freescale Semiconductor
1.7.2.7
PS[5:0] / KWS[5:0] — Port S I/O Signals
PS[5:0] are general-purpose input or output signals. The signals can be configured on per signal basis as
interrupt inputs with wake-up capability (KWS[5:0]). They can have a pull-up or pull-down device
selected and enabled on per signal basis. During and out of reset the pull-up devices are enabled.
1.7.2.8
PT[3:0] — Port T I/O Signals
PT[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. During and out of reset the pull devices are disabled.
1.7.2.9
AN0_[4:0], AN1_[3:0]— ADC Input Signals
These are the analog inputs of the Analog-to-Digital Converters. ADC0 has 5 analog input channels
connected to PAD port pins. ADC1 has 4 analog input channels connected to PAD port pins.
1.7.2.10
VRH, VRL — ADC Reference Signals
VRH and VRL are the reference voltage input pins for the analog-to-digital converter.
1.7.2.11
SPI0 Signals
1.7.2.11.1
SS0 Signal
This signal is associated with the slave select SS functionality of the serial peripheral interface SPI0.
1.7.2.11.2
SCK0 Signal
This signal is associated with the serial clock SCK functionality of the serial peripheral interface SPI0.
1.7.2.11.3
MISO0 Signal
This signal is associated with the MISO functionality of the serial peripheral interface SPI0. This signal
acts as master input during master mode or as slave output during slave mode.
1.7.2.11.4
MOSI0 Signal
This signal is associated with the MOSI functionality of the serial peripheral interface SPI0. This signal
acts as master output during master mode or as slave input during slave mode
1.7.2.12
SCI[1:0] Signals
1.7.2.12.1
RXD[1:0] Signals
These signals are associated with the receive functionality of the serial communication interfaces
(SCI[1:0]).
