Freescale Semiconductor MC9S12ZVM series, Reference Manual

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Chapter 12 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
428 Freescale Semiconductor
12.3.3 Programmer’s Model of Message Storage
The following section details the organization of the receive and transmit message buffers and the
associated control registers.
To simplify the programmer interface, the receive and transmit message buffers have the same outline.
Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last
two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an
internal timer after successful transmission or reception of a message. This feature is only available for
transmit and receiver buffers, if the TIME bit is set (see
Section 12.3.2.1, “MSCAN Control Register 0
(CANCTL0) ”).
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-23. CANIDMR0–CANIDMR3 Register Field Descriptions
Field Description
7-0
AM[7:0]
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
Module Base + 0x001C to Module Base + 0x001F Access: User read/write
(1)
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
7 6 5 4 3 2 1 0
R
AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0
W
Reset 0 0 0 0 0 0 0 0
Figure 12-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
Table 12-24. CANIDMR4–CANIDMR7 Register Field Descriptions
Field Description
7-0
AM[7:0]
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit