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Chapter 14 Pulse Width Modulator with Fault Protection (PMF15B6CV3)
MC9S12ZVM Family Reference Manual Rev. 1.3
498
Freescale Semiconductor
14.3.2.3
PMF Configure 2 Register (PMFCFG2)
4
TOPNEGC
Pair C Top-Side PWM Polarity — This bit determines the polarity for Pair C top-side PWM (PWM4). This bit
cannot be modified after the WP bit is set.
0 Positive PWM4 polarity
1 Negative PWM4 polarity
3
BOTNEGB
Pair B Bottom-Side PWM Polarity — This bit determines the polarity for Pair B bottom-side PWM (PWM3). This
bit cannot be modified after the WP bit is set.
0 Positive PWM3 polarity
1 Negative PWM3 polarity
2
TOPNEGB
Pair B Top-Side PWM Polarity — This bit determines the polarity for Pair B top-side PWM (PWM2). This bit
cannot be modified after the WP bit is set.
0 Positive PWM2 polarity
1 Negative PWM2 polarity
1
BOTNEGA
Pair A Bottom-Side PWM Polarity — This bit determines the polarity for Pair A bottom-side PWM (PWM1). This
bit cannot be modified after the WP bit is set.
0 Positive PWM1 polarity
1 Negative PWM1 polarity
0
TOPNEGA
Pair A Top-Side PWM Polarity — This bit determines the polarity for Pair A top-side PWM (PWM0). This bit
cannot be modified after the WP bit is set.
0 Positive PWM0 polarity
1 Negative PWM0 polarity
Address: Module Base + 0x0002
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
REV1
REV0
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
W
Reset
0
0
0
0
0
0
0
0
Figure 14-5. PMF Configure 2 Register (PMFCFG2)
Table 14-7. PMFCFG2 Field Descriptions
Field
Description
7-6
REV[1:0]
Select timebase counter to output reload event on pmf_reloada
These bits select if timebase generator A, B or C provides the reload event on output signal pmf_reloada.
00 Reload event generation disabled
01 PWM generator A generates reload event
10 PWM generator B generates reload event
11 PWM generator C generates reload event
Table 14-6. PMFCFG1 Field Descriptions (continued)
Field
Description