Chapter 11 Timer Module (TIM16B4CV3) Block Description
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
397
11.3.2.12 Timer Input Capture/Output Compare Registers High and Low 0–
3(TCxH and TCxL)
1
This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to
a reserved register have no functional effect. Reads from a reserved register return zeroes.
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
NOTE
Read/Write access in byte mode for high byte should take place before low
byte otherwise it will give a different result.
Module Base + 0x0010 = TC0H
0x0012 = TC1H
0x0014=TC2H
0x0016=TC3H
0x0018=RESERVD
0x001A=RESERVD
0x001C=RESERVD
0x001E=RESERVD
15
14
13
12
11
10
9
0
R
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
W
Reset
0
0
0
0
0
0
0
0
Figure 11-18. Timer Input Capture/Output Compare Register x High (TCxH)
Module Base + 0x0011 = TC0L
0x0013 = TC1L
0x0015 =TC2L
0x0017=TC3L
0x0019 =RESERVD
0x001B=RESERVD
0x001D=RESERVD
0x001F=RESERVD
7
6
5
4
3
2
1
0
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 11-19. Timer Input Capture/Output Compare Register x Low (TCxL)
