Chapter 11 Timer Module (TIM16B4CV3) Block Description
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
395
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
11.3.2.10 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
Table 11-12. Timer Clock Selection
PR2
PR1
PR0
Timer Clock
0
0
0
Bus Clock / 1
0
0
1
Bus Clock / 2
0
1
0
Bus Clock / 4
0
1
1
Bus Clock / 8
1
0
0
Bus Clock / 16
1
0
1
Bus Clock / 32
1
1
0
Bus Clock / 64
1
1
1
Bus Clock / 128
Module Base + 0x000E
7
6
5
4
3
2
1
0
R
RESERVED
RESERVED
RESERVED
RESERVED
C3F
C2F
C1F
C0F
W
Reset
0
0
0
0
0
0
0
0
Figure 11-16. Main Timer Interrupt Flag 1 (TFLG1)
Table 11-13. TRLG1 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field
Description
3:0
C[3:0]F
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN is set to one.
Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
