Chapter 1 Device Overview MC9S12ZVM-Family
MC9S12ZVM Family Reference Manual Rev. 1.3
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Freescale Semiconductor
1.7.2.18.2
ECLK
This signal is associated with the output of the bus clock (ECLK).
NOTE
This feature is only intended for debug purposes at room temperature.
It must not be used for clocking external devices in an application.
1.7.2.19
BDC and Debug Signals
1.7.2.19.1
BKGD — Background Debug signal
The BKGD signal is used as a pseudo-open-drain signal for the background debug communication. The
BKGD signal has an internal pull-up device.
1.7.2.19.2
PDO — Profiling Data Output
This is the profiling data output signal used when the DBG module profiling feature is enabled. This signal
is output only and provides a serial, encoded data stream that can be used by external development tools
to reconstruct the internal CPU code flow.
1.7.2.19.3
PDOCLK — Profiling Data Output Clock
This is the PDO clock signal used when the DBG module profiling feature is enabled. This signal is output
only. During code profiling this is the clock signal that can be used by external development tools to sample
the PDO signal.
1.7.2.19.4
DBGEEV — External Event Input
This signal is the DBG external event input. It is input only. Within the DBG module, it allows an external
event to force a state sequencer transition, or trace buffer entry, or to gate trace buffer entries. A falling
edge at the external event signal constitutes an event. Rising edges have no effect. The maximum frequency
of events is half the internal core bus frequency.
1.7.2.20
FAULT5
— External Fault Input
This is the PMF fault input signal, with configurable polarity, that can be used to disable PMF operation
when asserted. Asynchronous shutdown of the GDU outputs HG[2:0] and LG[2:0] is not supported. Select
QSMPm[1:0] > 0 in PMF.
1.7.2.21
LIN Physical Layer Signals
1.7.2.21.1
LIN0
This pad is connected to the single-wire LIN data bus. This signal is only available on S12ZVML versions.
1.7.2.21.2
LP0TXD
This is the LIN physical layer transmitter input signal.
