MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
243
Chapter 8
S12 Clock, Reset and Power Management Unit
(S12CPMU_UHV_V6)
Revision History
8.1
Introduction
This specification describes the function of the Clock, Reset and Power Management Unit
(S12CPMU_UHV_V6).
•
The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock
source. It is designed for optimal start-up margin with typical crystal oscillators.
•
The Voltage regulator (VREGAUTO) operates from the range 6V to 18V. It provides all the
required chip internal voltages and voltage monitors.
•
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
•
The Internal Reference Clock (IRC1M) provides a 1MHz internal clock.
Rev. No.
(Item No)
Date
(Submitted By)
Sections Affected
Substantial Change(s)
V06.02
20 Dec. 2012
• Format and font corrections
• Table 8-31. CPMUOSC2 Field Descriptions: removed Bit6 and
Bit4-0 description as these bits no longer exist.
V06.03
18 June 2013
• EXTCON register Bit: correct reset value to 1
• PMRF register Bit: corrected description
• Memory map: corrected address typo CPMUAPIRH register
V06.04
21 Aug. 2013
• corrected bit numbering for CSAD Bit
• f
PLLRST
changed to f
VCORST
• corrected typo in heading of CPMUOSC2 Field Description
• changed frequency upper limit of external Pierce Oscillator
V06.05
3 Jan. 2014
