Freescale Semiconductor MC9S12ZVM series, Reference Manual

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Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor 257
frequency as shown in Table 8-2 . Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional
PLL (no locking and/or insufficient stability).
8.3.2.3 S12CPMU_UHV_V6 Reference Divider Register (CPMUREFDIV)
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the
external oscillator as reference.
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in
Table 8-3 .
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= f
REF
<=
2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
Table 8-2. VCO Clock Frequency Selection
VCOCLK Frequency Ranges VCOFRQ[1:0]
32MHz <= f
VCO
<= 48MHz 00
48MHz < f
VCO
<= 80MHz 01
Reserved 10
80MHz < f
VCO
<= 100MHz 11
Module Base + 0x0005
7 6 5 4 3 2 1 0
R
REFFRQ[1:0]
0 0
REFDIV[3:0]
W
Reset 0 0 0 0 1 1 1 1
Figure 8-6. S12CPMU_UHV_V6 Reference Divider Register (CPMUREFDIV)
f
REF
f
OSC
REFDIV 1
+
( )
------------------------------------ =
If XOSCLCP is enabled (OSCE=1)
If XOSCLCP is disabled (OSCE=0)
f
REF
f
IRC1M
=