X20 system modules • X20 electronics module communication • X20CS1011
X20 system User's Manual 3.10
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4.18.2.8.7 Status of all slaves
Name:
SlaveStatus
The current state of the slave is indicated collectively in this register.
In the event of an error, the failed slaves are indicated in the respective bits, and in the status registers individually
set up for the slaves (see 4.18.2.8.13.1 "SlaveStatus1 to SlaveStatus16").
Data is exchanged cyclically as long as none of these bits are set. If an error does error, then I/O transfer is
stopped. The bus can be started again after the error has been corrected or a setup has been performed again
(see 4.18.2.8.12 "Basic application registers "SmartWireEnable" and "SmartWireMode"").
Data type
Value
UINT
See bit structure.
Bit structure:
Bit
Description
Value
Information
0
Ok
0
Slave 1
1
Errors
...
...
0
Ok
15
Slave 16
1
Errors
4.18.2.8.8 Transfer control bits to slaves
Name:
FastOutput01_02 to FastOutput15_16
In these registers, the control bits are transferred to 2 consecutive slaves. Each slave receives 4 control bits, that
must be selected from the 8 data bytes depending on the node address (1 to 16). These 4 control bits are assigned
fixed values and utilization of the bits by the slave is optional.
All of the slaves evaluate this telegram. It must be sent cyclically by the master so that the slaves can ensure that
the master is still functioning without any problems within the monitoring time (lifeguarding time = 400 ms).
Data type
Value
USINT
See bit structure.
Bit structure:
Bit
Description
Value
Information
0
Digital output 1 reset
0
Slave N
1
Digital output 1 set
...
..
0
Digital output 4 reset
3
Slave N
1
Digital output 4 set
0
Digital output 1 reset
4
Slave N + 1
1
Digital output 1 set
...
..
0
Digital output 4 reset
7
Slave N + 1
1
Digital output 4 set
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