DocID018909 Rev 11
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RM0090
Memory and bus architecture
112
0x4000 7400 - 0x4000 77FF
DAC
APB1
Section 14.5.15: DAC register map on page 455
0x4000 7000 - 0x4000 73FF
PWR
Section 5.6: PWR register map on page 149
0x4000 6800 - 0x4000 6BFF
CAN2
Section 32.9.5: bxCAN register map on page 1109
0x4000 6400 - 0x4000 67FF
CAN1
0x4000 5C00 - 0x4000 5FFF
I2C3
Section 27.6.11: I2C register map on page 864
0x4000 5800 - 0x4000 5BFF
I2C2
0x4000 5400 - 0x4000 57FF
I2C1
0x4000 5000 - 0x4000 53FF
UART5
Section 30.6.8: USART register map on page 1010
0x4000 4C00 - 0x4000 4FFF
UART4
0x4000 4800 - 0x4000 4BFF
USART3
0x4000 4400 - 0x4000 47FF
USART2
0x4000 4000 - 0x4000 43FF
I2S3ext
Section 28.5.10: SPI register map on page 918
0x4000 3C00 - 0x4000 3FFF
SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF
SPI2 / I2S2
0x4000 3400 - 0x4000 37FF
I2S2ext
0x4000 3000 - 0x4000 33FF
IWDG
Section 21.4.5: IWDG register map on page 703
0x4000 2C00 - 0x4000 2FFF
WWDG
Section 22.6.4: WWDG register map on page 710
0x4000 2800 - 0x4000 2BFF RTC & BKP Registers
Section 26.6.21: RTC register map on page 826
0x4000 2000 - 0x4000 23FF
TIM14
Section 19.5.12: TIM10/11/13/14 register map on
page 686
0x4000 1C00 - 0x4000 1FFF
TIM13
0x4000 1800 - 0x4000 1BFF
TIM12
Section 19.4.13: TIM9/12 register map on
page 675
0x4000 1400 - 0x4000 17FF
TIM7
Section 20.4.9: TIM6&TIM7 register map on
page 698
0x4000 1000 - 0x4000 13FF
TIM6
0x4000 0C00 - 0x4000 0FFF
TIM5
Section 18.4.21: TIMx register map on page 639
0x4000 0800 - 0x4000 0BFF
TIM4
0x4000 0400 - 0x4000 07FF
TIM3
0x4000 0000 - 0x4000 03FF
TIM2
Table 1. STM32F4xx register boundary addresses (continued)
Boundary address
Peripheral
Bus
Register map