Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
RM0090
200/1731
DocID018909 Rev 11
6.3.21
RCC clock control & status register (RCC_CSR)
Address offset: 0x74
Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.
Access: 0
≤
wait state
≤
3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Bits 9:8
RTCSEL[1:0]:
RTC clock source selection
These bits are set by software to select the clock source for the RTC. Once the RTC clock
source has been selected, it cannot be changed anymore unless the Backup domain is
reset. The BDRST bit can be used to reset them.
00: No clock
01: LSE oscillator clock used as the RTC clock
10: LSI oscillator clock used as the RTC clock
11: HSE oscillator clock divided by a programmable prescaler (selection through the
RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC
clock
Bits 7:3 Reserved, must be kept at reset value.
Bit 2
LSEBYP:
External low-speed oscillator bypass
This bit is set and cleared by software to bypass the oscillator. This bit can be written only
when the LSE clock is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1
LSERDY:
External low-speed oscillator ready
This bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is
stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed
oscillator clock cycles.
0: LSE clock not ready
1: LSE clock ready
Bit 0
LSEON:
External low-speed oscillator enable
This bit is set and cleared by software.
0: LSE clock OFF
1: LSE clock ON
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LPWR
RSTF
WWDG
RSTF
IWDG
RSTF
SFT
RSTF
POR
RSTF
PIN
RSTF
BORRS
TF
RMVF
Reserved
r
r
r
r
r
r
r
rt_w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
LSIRDY LSION
r
rw
