STMicroelectronics STM32F405, Reference Manual

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Revision history RM0090
1720/1731 DocID018909 Rev 11
14-Oct-2014
8
(continued)
FMC :
Modified step 7 in Section : SDRAM initialization .
Modified SDRAM refresh rate equations and example in Section :
SDRAM Refresh Timer register (FMC_SDRTR) and updated
definition of COUNT bits.
Updated EXTMOD definition in
Section : SRAM/NOR-Flash chip-
select control registers 1..4 (FMC_BCR1..4) .
Updated ADDSET definition in Section : SRAM/NOR-Flash chip-
select timing registers 1..4 (FMC_BTR1..4) and Section :
SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4) .
Table 310. Document revision history (continued)
Date Ver s ion Chan g e s