STMicroelectronics STM32F405, Reference Manual

Page: 1124 / 1731

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
1124/1731 DocID018909 Rev 11
RMII clock sources
Either clock the PHY from an external 50 MHz clock or use a PHY with an embedded PLL to
generate the 50 MHz frequency.
Figure 357. RMII clock sources
33.4.4 MII/RMII selection
The mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the
SYSCFG_PMC register. The application has to set the MII/RMII mode while the Ethernet
controller is under reset or before enabling the clocks.
MII/RMII internal clock scheme
The clock scheme required to support both the MII and RMII, as well as 10 and 100 Mbit/s
operations is described in
Figure 358 .
Figure 358. Clock scheme
1. The MII/RMII selection is controlled through bit 23, MII_RMII_SEL, in the SYSCFG_PMC register.
To save a pin, the two input clock signals, RMII_REF_CK and MII_RX_CLK, are multiplexed
on the same GPIO pin.
069
670
0&8
5()B&/.
0+]
0+]
3//
)RU0ELWV
([WHUQDO
3+<
0$&
GPIO and AF
controller
GPIO and AF
controller
MII_TX_CLK as AF
(25 MHz or 2.5 MHz)
MII_RX_CLK as AF
(25 MHz or 2.5 MHz)
Sync. divider
/2 for 100 M
b /s
/20 for 10 M b /s
50 MHz
0
1
0
1
25 MHz or 2.5 MHz
25 MHz or 2.5 MHz
0 MII
1 RMII
(1)
25 MHz
or 2.5 MHz
25 MHz
or 2.5 MHz
MACTXCLK
MACRXCLK
TX
RX
AHB
HCLK
HCLK
MAC
must b e greater
than 25 MHz
ai15650
RMII
RMII_REF_CK as AF
(50 MHz)