DocID018909 Rev 11
143/1731
RM0090
Power controller (PWR)
149
Bits 13:10 Reserved, must be kept at reset value.
Bit 9
BRE
: Backup regulator enable
When set, the Backup regulator (used to maintain backup SRAM content in Standby and
V
BAT
modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup
SRAM can still be used but its content will be lost in the Standby and V
BAT
modes. Once set,
the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
the data written into the RAM will be maintained in the Standby and V
BAT
modes.
0: Backup regulator disabled
1: Backup regulator enabled
Note: This bit is not reset when the device wakes up from Standby mode, by a system reset,
or by a power reset.
Bit 8
EWUP
: Enable WKUP pin
This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup
the device from Standby mode.
1: WKUP pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
Bits 7:4 Reserved, must be kept at reset value.
Bit 3
BRR
: Backup regulator ready
Set by hardware to indicate that the Backup Regulator is ready.
0: Backup Regulator not ready
1: Backup Regulator ready
Note: This bit is not reset when the device wakes up from Standby mode or by a system reset
or power reset.
Bit 2
PVDO:
PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: V
DD
is higher than the PVD threshold selected with the PLS[2:0] bits.
1: V
DD
is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Standby or reset until the PVDE bit is set.
Bit 1
SBF:
Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down
reset) or by setting the CSBF bit in the PWR_CR register.
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0
WUF:
Wakeup flag
This bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in
the PWR_CR register.
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or
Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).
Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
EWUP bit) when the WKUP pin level is already high.