USB on-the-go full-speed (OTG_FS)
RM0090
1300/1731
DocID018909 Rev 11
OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
Address offset: 0x900
Reset value: 0x0000 0000
This section describes the OTG_FS_DIEPCTL0 register. Nonzero control endpoints use
registers for endpoints 1–3.
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0
INEPTXFEM:
IN EP Tx FIFO empty interrupt mask bits
These bits act as mask bits for OTG_FS_DIEPINTx.
TXFE interrupt one bit per IN endpoint:
Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3
0: Masked interrupt
1: Unmasked interrupt
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
E
PENA
EPDI
S
Re
se
rved
SN
A
K
CN
A
K
TXFNUM
ST
A
L
L
Re
se
rved
EPTYP
NAKS
TS
Re
se
rved
USB
AEP
Reserved
MPSIZ
r
r
w
w
rw rw rw rw
rs
r
r
r
r
rw rw
Bit 31
EPENA:
Endpoint enable
The application sets this bit to start transmitting data on the endpoint 0.
The core clears this bit before setting any of the following interrupts on this endpoint:
– Endpoint disabled
– Transfer completed
Bit 30
EPDIS:
Endpoint disable
The application sets this bit to stop transmitting data on an endpoint, even before the
transfer for that endpoint is complete. The application must wait for the Endpoint disabled
interrupt before treating the endpoint as disabled. The core clears this bit before setting the
Endpoint disabled interrupt. The application must set this bit only if Endpoint enable is
already set for this endpoint.
Bits 29:28 Reserved, must be kept at reset value.
Bit 27
SNAK:
Set NAK
A write to this bit sets the NAK bit for the endpoint.
Using this bit, the application can control the transmission of NAK handshakes on an
endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on
that endpoint.
Bit 26
CNAK:
Clear NAK
A write to this bit clears the NAK bit for the endpoint.
Bits 25:22
TXFNUM:
TxFIFO number
This value is set to the FIFO number that is assigned to IN endpoint 0.
Bit 21
STALL:
STALL handshake
The application can only set this bit, and the core clears it when a SETUP token is received
for this endpoint. If a NAK bit, a Global IN NAK or Global OUT NAK is set along with this bit,
the STALL bit takes priority.