DocID018909 Rev 11
RM0090
USB on-the-go high-speed (OTG_HS)
1529
Soft disconnect
The Powered state can be exited by software by using the soft disconnect feature. The DP
pull-up resistor is removed by setting the Soft disconnect bit in the device control register
(SDIS bit in OTG_HS_DCTL), thus generating a device disconnect detection interrupt on
the host side even though the USB cable was not really unplugged from the host port.
Default state
In Default state the OTG_HS expects to receive a SET_ADDRESS command from the host.
No other USB operations are possible. When a valid SET_ADDRESS command is decoded
on the USB, the application writes the corresponding number into the device address field in
the device configuration register (DAD bit in OTG_HS_DCFG). The OTG_HS then enters
the address state and is ready to answer host transactions at the configured USB address.
Suspended state
The OTG_HS peripheral constantly monitors the USB activity. When the USB remains idle
for 3 ms, the early suspend interrupt (ESUSP bit in OTG_HS_GINTSTS) is issued. It is
confirmed 3 ms later, if appropriate, by generating a suspend interrupt (USBSUSP bit in
OTG_HS_GINTSTS). The device suspend bit is then automatically set in the device status
register (SUSPSTS bit in OTG_HS_DSTS) and the OTG_HS enters the Suspended state.
The device can also exit from the Suspended state by itself. In this case the application sets
the remote wakeup signaling bit in the device control register (RWUSIG bit in
OTG_HS_DCTL) and clears it after 1 to 15 ms.
When a resume signaling is detected from the host, the resume interrupt (WKUPINT bit in
OTG_HS_GINTSTS) is generated and the device suspend bit is automatically cleared.
35.5.3 Peripheral
endpoints
The OTG_HS core instantiates the following USB endpoints:
•
Control endpoint 0
This endpoint is bidirectional and handles control messages only.
It has a separate set of registers to handle IN and OUT transactions, as well as
dedicated control (OTG_HS_DIEPCTL0/OTG_HS_DOEPCTL0), transfer configuration
(OTG_HS_DIEPTSIZ0/OTG_HS_DIEPTSIZ0), and status-interrupt
(OTG_HS_DIEPINTx/)OTG_HS_DOEPINT0) registers. The bits available inside the
control and transfer size registers slightly differ from other endpoints.
•
5 IN endpoints
–
They can be configured to support the isochronous, bulk or interrupt transfer type.
–
They feature dedicated control (OTG_HS_DIEPCTLx), transfer configuration
(OTG_HS_DIEPTSIZx), and status-interrupt (OTG_HS_DIEPINTx) registers.
–
The Device IN endpoints common interrupt mask register (OTG_HS_DIEPMSK)
allows to enable/disable a single endpoint interrupt source on all of the
IN endpoints (EP0 included).
–
They support incomplete isochronous IN transfer interrupt (IISOIXFR bit in
OTG_HS_GINTSTS). This interrupt is asserted when there is at least one
isochronous IN endpoint for which the transfer is not completed in the current
