USB on-the-go high-speed (OTG_HS)
RM0090
1386/1731
DocID018909 Rev 11
are enabled, at least two spaces of (Largest Packet Size / 4) + 1 must be allocated to
receive back-to-back packets. Typically, two (Largest Packet Size / 4) + 1 spaces are
recommended so that when the previous packet is being transferred to AHB, the USB can
receive the subsequent packet.
Along with each host channels last packet, transfer complete status information are also
pushed to the FIFO. As a consequence, one location must be allocated to store this data.
Transmit FIFO RAM
For Transmit FIFO RAM allocation, the minimum amount of RAM required for the host
nonperiodic Transmit FIFO is the largest maximum packet size for all supported nonperiodic
OUT channels. Typically, a space corresponding to two Largest Packet Size is
recommended, so that when the current packet is being transferred to the USB, the AHB
can transmit the subsequent packet.
The minimum amount of RAM required for Host periodic Transmit FIFO is the largest
maximum packet size for all supported periodic OUT channels. If there is at least one High
Bandwidth Isochronous OUT endpoint, then the space must be at least two times the
maximum packet size for that channel.
Note:
More space allocated in the Transmit nonperiodic FIFO results in better performance on the
USB.
When operating in DMA mode, the DMA address register for each host channel (HCDMAn)
is stored in the SPRAM (FIFO). One location for each channel must be reserved for this.
35.11 OTG_HS
interrupts
When the OTG_HS controller is operating in one mode, either peripheral or host, the
application must not access registers from the other mode. If an illegal access occurs, a
mode mismatch interrupt is generated and reflected in the Core interrupt register (MMIS bit
in the OTG_HS_GINTSTS register). When the core switches from one mode to the other,
the registers in the new mode of operation must be reprogrammed as they would be after a
power-on reset.
